Song Han is an assistant professor in the Electrical Engineering and Computer Science Department of the Massachusetts Institute of Technology (MIT). Dr. Han received the Ph.D. degree in Electrical Engineering from Stanford University advised by Prof. Bill Dally. His industry experiences include Google Brain and Facebook Applied Machine Learning.
Dr. Han’s research focuses on energy-efficient deep learning, at the intersection between machine learning and computer architecture. He proposed Deep Compression that can compress deep neural networks by an order of magnitude without losing the prediction accuracy. He designed EIE: Efficient Inference Engine, a hardware accelerator that can perform inference directly on the compressed sparse model, which saves memory bandwidth and results in significant speedup and energy saving. His work has been featured by TheNextPlatform, TechEmergence, Embedded Vision and O’Reilly. His research efforts in model compression and hardware acceleration received the Best Paper Award at ICLR’16 and the Best Paper Award at FPGA’17. Before joining Stanford, Song graduated from Tsinghua University.
I joined MIT EECS as an assistant professor (MIT news). My recent research focus on Hardware-Centric AutoML for computation-intensive AI applications. I am looking for PhD students interested in deep learning and computer architecture. Below are the missions of HAN Lab:
H: High performance, High energy efficiency Hardware
A: AutoML, Architectures and Accelerators for AI
N: Novel algorithms for Neural Networks
In the post-ImageNet era, computer vision and machine learning researchers are solving more complicated AI problems using larger data sets driving the demand for more computation. However, Moore’s Law is slowing down, and the amount of computation per unit cost and power is no longer increasing at its historic rate. This mismatch between supply and demand for computation highlights the need for co-designing efficient machine learning algorithms and domain-specific hardware architectures. The vast design space across algorithm and hardware is difficult to be explored by human engineers. Therefore, we need hardware-centric AutoML and design automation for deep learning computing to bridge the gap. Our recent work on Hardware-Centric AutoML: [ProxylessNAS][AMC][HAQ]
I’m interested in application-driven, domain-specific computer architecture research. I’m interested in achieving higher efficiency by tailoring the hardware architecture to characteristics of the application domain (videos, 3D), and also innovating on efficient algorithms that are hardware-friendly. My current research center around co-designing efficient algorithms and hardware systems for machine learning, to free AI from the power hungry hardware beasts and democratize AI to cheap mobile devices, reducing the cost of running deep learning on data centers, as well as automating machine learning model design. I enjoy the research intersections across machine learning algorithms and computer architecture.
- Dec 2018: Our work on Learning to Design Circuits appeared at NeurIPS workshop on Machine Learning for Systems. Analog IC design relies on human experts to search for parameters that satisfy circuit specifications with their experience and intuitions, which is highly labor intensive, time consuming and suboptimal. This paper propose a learning based approach to optimize circuit parameters. [paper][website]
- Dec 2018: Our work on HAQ: Hardware-aware Automated Quantization appeared at NeurIPS workshop on Machine Learning on the Phone and other Consumer Devices. HAQ leverages the reinforcement learning to automatically determine the quantization policy (bit width per layer), and we take the hardware accelerator’s feedback in the design loop. Rather than relying on proxy signals such as FLOPs and model size, we employ a hardware simulator to generate direct feedback (latency cycles, energy, etc) to the RL agent. Compared with conventional methods, our framework is fully automated and can specialize the quantization policy for different neural network architectures and hardware architectures. [paper][website]
- Dec 2018: Our work on ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware is accepted by ICLR’19. Neural Architecture Search (NAS) is computation intensive. ProxylessNAS saves the GPU hours by 200x than NAS, saves GPU memory by 10x than DARTS, while directly searching on ImageNet. ProxylessNAS is hardware-aware. It can design specialized neural network architecture for different hardware, making inference fast. With >74.5% top-1 accuracy, the measured latency of ProxylessNAS is 1.8x faster than MobileNet-v2, the current industry standard for mobile vision. [paper][code][demo][website]
- Nov 2018: Our work on Efficient Video Understanding with Temporal Shift Module (TSM) is available on arXiv. Video understanding is more computation intensive than images and it is expensive to deploy. TSM uses 2D convolution’s computation complexity and achieves better temporal modeling ability than 3D convolution. Measured on P100 GPU, TSM achieved 1.8% higher accuracy at 8x lower latency and 12x higher throughput compared with I3D. TSM ranks the first on both Something-Something V1 and V2 leaderboards as of Nov 2018. [paper][website][demo][slides]
- Sep 2018: Song Han received Amazon Machine Learning Research Award.
- Sep 2018: Song Han received SONY Faculty Award.
- Sep 2018: Our work on AMC: AutoML for Model Compression and Acceleration on Mobile Devices is accepted by ECCV’18. This paper proposes learning-based method to perform model compression, rather than relying on human heuristics and rule-based methods. AMC can automate the model compression process, achieve better compression ratio, and also be more sample efficient. It takes shorter time can do better than rule-based heuristics. AMC compresses ResNet-50 by 5x without losing accuracy. AMC makes MobileNet-v1 2x faster with 0.4% loss of accuracy. [paper / bibTeX]
- June 2018: Song presents invited paper “Bandwidth Efficient Deep Learning” at Design Automation Conference (DAC’18). The paper talks about techniques to save memory bandwidth, networking bandwidth, and engineer bandwidth for efficient deep learning.
- Mar 26, 2018: Song presented Deep Gradient Compression at NVIDIA GPU Technology Conference.
- Feb 26, 2018: Song presented “Bandwidth Efficient Deep Learning: Challenges and Trade-offs” at FPGA’18 panel session.
- Jan 29, 2018: Deep Gradient Compression is accepted by ICLR’18. This technique can reduce the communication bandwidth by 500x and improves the scalability of large-scale distributed training. [slides].
- Ph.D. Stanford University, Sep. 2012 to Sep. 2017
- B.S. Tsinghua University, Aug. 2008 to Jul. 2012
- Email: FirstnameLastname [at] mit [dot] edu
- PhD and summer intern applicants: please email han [dot] lab [dot] mit [at] gmail so that it won’t be filtered.