Song Han is an assistant professor in the Electrical Engineering and Computer Science Department of the Massachusetts Institute of Technology (MIT). Dr. Han received the Ph.D. degree in Electrical Engineering from Stanford University advised by Prof. Bill Dally. His industry experiences include Google Brain and Facebook AML (Applied Machine Learning). Dr. Han co-founded DeePhi Tech in 2016, a startup offering efficient solutions for deep learning computing (deep compression and hardware acceleration).

Dr. Han’s research focuses on energy-efficient deep learning, at the intersection between machine learning and computer architecture. He proposed Deep Compression that can compress deep neural networks by an order of magnitude without losing the prediction accuracy. He designed EIE: Efficient Inference Engine, a hardware accelerator that can perform inference directly on the compressed sparse model, which saves memory bandwidth and results in significant speedup and energy saving. His work has been featured by TheNextPlatform, TechEmergence, Embedded Vision and O’Reilly. His research efforts in model compression and hardware acceleration received the Best Paper Award at ICLR’16 and the Best Paper Award at FPGA’17. Before joining Stanford, Song graduated from Tsinghua University.
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I joined MIT EECS as an assistant professor (MIT news). I am looking for PhD students interested in deep learning and computer architecture. Below are the missions of HAN’s Lab:

H: High performance, High energy efficiency Hardware

A: Architectures and Accelerators for Artificial Intelligence

N: Novel algorithms for Neural Networks and deep learning

S: Small models, Scalable Systems, and Specialized Silicon

In the post-ImageNet era, computer vision and machine learning researchers are solving more complicated AI problems using larger data sets driving the demand for more computation.
However, we are in the post-Moore’s Law world where the amount of computation per unit cost and power is no longer increasing at its historic rate. This mismatch between supply and demand for computation highlights the need for co-designing efficient machine learning algorithms and domain-specific hardware architectures.


  • Ph.D. Stanford University, Sep. 2012 to Sep. 2017
  • M.S. Stanford University, Sep. 2012 to Jun. 2014
  • B.S. Tsinghua University, Aug. 2008 to Jul. 2012


  • TPC member for the 23rd IEEE Symposium on High Performance Computer Architecture
  • Reviewer for Journal of Machine Learning Research (JMLR)
  • Reviewer for IEEE Transactions on Neural Networks and Learning Systems (TNNLS)
  • Reviewer for Computer Vision and Image Understanding (CVIU)
  • Reviewer for IEEE Journal of Solid State Circuits (JSSCC)
  • Reviewer for IEEE Micro
  • Reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems (TCAD)
  • Reviewer for ACM Journal on Emerging Technologies in Computing Systems (JETC)
  • Reviewer for IEEE Embedded Systems Letters (ESL)
  • Reviewer for 30th Annual Conference on Neural Information Processing Systems (NIPS)
  • Reviewer for 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)


  • Email: FirstnameLastname [at] mit [dot] edu
  • Office: 50 Vassar Street, Building 38-344, Cambridge, MA